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ic-mh 12 bit angular hall encoder rev b1, page 1/ 23 features ? real-time system for rotation speed up to 120,000 rpm ? integrated hall sensors with automatic offset compensation ? 4x sensor arrangement for fault-tolerant adjustment ? amplitude control for optimum operating point ? interpolator with 4096 angular increments/resolution better than 0.1 ? programmable resolution, hysteresis, edge spacing, zero position and rotating direction ? incremental output of sensor position up to 8 mhz edge rate ? rs422-compatible ab encoder signals with index z ? uvw commutation signals for ec motor applications ? serial interface for data output and con?guration ? ssi-compatible output mode ? integrated zap diodes for module setup and oem data, programmable via serial interface ? signal error (e.g. magnet loss) can also be read out via serial interface ? extended temperature range from -40 to +125 c applications ? digital angular sensor technology, 0C360 ? incremental angular encoder ? absolute angular encoder ? brushless motors ? motor feedback ? rotational speed control packages qfn28 5 x 5 mm2 block diagram copyright ? 2008 ic-haus http://www.ichaus.com 2 2 s l i s l o m a p t e n e r r v p a v p d a b z u v w v n a v n d b b b b l o g ic c o n v e r s io n p h a s e s h if t v z a p t e s t e r r o r m o n i t o r i n c r i n t e r f a c e s i n e - t o - d i g s i n e - t o - c o m h a l l s e n s o r a m p l c o n t r o l r a m b i a s / v r e f z a p r o m r s 4 2 2 z a p c o n t r o l 1 6 b y te z r o m 0 x 0 0 0 x 7 f s in + c o s a m p l it u d e c o r r e c t io n i n t e r f a c e s e r i a l 0 x 0 f 0 x 1 0 0 x 1 f 0 x 7 7 + 5v + 5v ic-mh c301107-2
ic-mh 12 bit angular hall encoder rev b1, page 2/ 23 description the ic-mh 12-bit angular encoder is a position sen- sor with integrated hall sensors for scanning a per- manent magnet. the signal conditioning unit gen- erates constant-amplitude sine and cosine voltages that can be used for angle calculation. the resolu- tion can be programmed up to a maximum of 4,096 angular increments per rotation. the integrated serial interface also enables the posi- tion data to be read out to several networked sensors. and the integrated memory can be written embedded in the data protocol. the incremental interface with the pins a, b and z supplies quadrature signals with an edge rate of up to 8 mhz. interpolation can be carried out with maxi- mum resolution at a speed of 120,000 rpm. the po- sition of the index pulse z is adjustable. the commutation interface with the signals u, v and w provides 120 phase-shifted signals for block com- mutation. the zero point of the commutation signals is freely de?nable in increments of 1.875 over 360. the commutation signals are available for ec motors with 1 and 2 pole pairs. the rs422-compatible outputs of the incremental interface and the commutation interface are pro- grammable in the output current and the slew rate. in conjunction with a rotating permanent magnet, the ic-mh module forms a one-chip encoder. the entire con?guration can be stored in the internal parameter rom with zapping diodes. the integrated program- ming algorithm assumes writing of the rom struc- ture. packages qfn28 5 x5 mm2 to jedec mo-220-vhhd-1 pin configuration qfn28 5 x 5mm2 pin functions no. name function 1 pte test enable pin 2 nerr error output(active low) 3 vpa +5 v supply voltage (analog) 4 vna ground (analog) 5 sli serial interface, data input 6 ma serial interface, clock input 7 slo serial interface, data output 8-11 nc not connected 12 vzap zener zapping programming voltage 13,14 nc not connected 15 a incremental a (+nu) 16 b incremental b (+nv) 17 z index z (+nw) 18 vnd ground (digital) 19 vpd +5 v supply voltage (digital) 20 u commutation u (+na) 21 v commutation v (+nb) 22 w commutation w (+nz) 23-28 nc not connected tp thermal-pad the thermal pad is to be connected to vna on the pcb. orientation of the logo ( mh code ...) is subject to alteration. m h 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 p t e n e r r v p a v n a s l i m a s l o v w nc nc nc nc nc nc nc nc nc nc nc nc v z a p u v p d v n d z b a
ic-mh 12 bit angular hall encoder rev b1, page 3/ 23 absolute maximum ratings beyond these values damage may occur; device operation is not guaranteed. item symbol parameter conditions unit no. min. max. g001 v() supply voltages at vpa, vpd -0.3 6 v g002 v(vzap) zapping voltage -0.3 8 v g003 v() voltages at a, b, z, u, v, w, ma, slo, sli, nerr, pte -0.3 6 v g004 i() current in vpa -10 20 ma g005 i() current in vpd -20 200 ma g006 i() current in a, b, z, u, v, w -100 100 ma g007 i() current in ma, slo, sli, nerr, pte -10 10 ma g008 vd() esd-voltage, all pins hbm 100 pf discharged over 1.5 k 2 kv g009 ts storage temperature -40 150 c g010 tj chip temperature -40 135 c thermal data operating conditions: vpa, vpd = 5 v 10 % item symbol parameter conditions unit no. min. typ. max. t01 ta ambient temperature -40 125 c t02 rthja thermal resistance chip/ambient package mounted on pcb, thermal pad at 40 k/w approx. 2 cm2 cooling area all voltages are referenced to ground unless otherwise stated. all currents into the device pins are positive; all currents out of the device pins are negative.
ic-mh 12 bit angular hall encoder rev b1, page 4/ 23 electrical characteristics operating conditions: vpa, vpd = 5 v 10 %, tj = -40...125 c, ibm adjusted to 200 a , 4 mm ndfeb magnet, unless otherwise noted item symbol parameter conditions unit no. min. typ. max. general 001 v(vpa, vpd) supply voltage range 4.5 5.5 v 002 i(vpa) supply current in vpa 3 8 ma 003 i(vpd) supply current in vpd prm = 0, without load 5 15 ma 004 i(vpd) supply current in vpd prm = 1, without load 2 10 ma 005 vc(hi) clamp voltage hi at ma, sli, slo, pte, nerr vc()hi = v() ? vpd, i() = 1 ma 0.4 1.5 v 006 vc(lo) clamp voltage lo i() = -1 ma -1.5 -0.3 v hall sensors and signal conditioning 101 hext operating magnetic field strength at chip surface 20 100 ka/m 102 fmag operating magnetic field fre- quency rotating speed of magnet 2 120 000 khz rpm 103 dsens diameter of hall sensor array 2 mm 104 xdis lateral displacement of magnet to chip 0.2 mm 105 xpac displacement chip to package qfn28 package -0.2 0.2 mm 106 pac angular alignment of chip vs. package qfn28 package -3 +3 deg 107 hpac distance of chip surface to pack- age surface qfn28 package 0.4 mm 108 vos trimming range of output offset voltage voss or vosc = 0x7f -55 mv 109 vos trimming range of output offset voltage voss or vosc = 0x3f 55 mv 110 vopt optimal differential output voltage vopt = vpp(psin) ? vpp(nsin), enac = 0, see fig. 6 4 vpp amplitude control 201 vampl differential output amplitude vampl = vpp(psin) ? vpp(nsin), enac = 1, see fig. 6 3.2 4.8 vpp 202 vratio amplitude ratio vratio = vpp(psin) / vpp(pcos) 1.09 203 vratio amplitude ratio vratio = vpp(psin) / vpp(pcos) 0.91 204 tampl settling time of amplitude con- trol 10% 300 s 205 vae()lo amplitude error threshold for minerr vpp(psin) ? vpp(nsin) 1.2 2.8 vpp 206 vae()hi amplitude error threshold for maxerr vpp(psin) ? vpp(nsin) 5.0 5.8 vpp bandgap reference 401 vbg bandgap reference voltage 1.2 1.25 1.3 v 402 vref reference voltage 45 50 55 %vpa 403 iibm bias current cibm = 0x0 -100 a cibm = 0xf -370 a bias current adjusted -220 -200 -180 a 404 vpdon turn-on threshold vpd, system on v(vpd) ? v(vnd), increasing voltage 3.7 4.0 4.3 v 405 vpdoff turn-off threshold vpd, system reset v(vpd) ? v(vnd), decreasing voltage 3 3.5 3.8 v 406 vpdhys hysteresis system on/reset 0.35 v 407 vosr reference voltage offset com- pensation 480 500 520 mv
ic-mh 12 bit angular hall encoder rev b1, page 5/ 23 electrical characteristics operating conditions: vpa, vpd = 5 v 10 %, tj = -40...125 c, ibm adjusted to 200 a , 4 mm ndfeb magnet, unless otherwise noted item symbol parameter conditions unit no. min. typ. max. clock generation 501 f()sys system clock bias current adjusted 0.85 1.0 1.15 mhz 502 f()sdc sinus/digital-converter clock bias current adjusted 14 16 18 mhz sin/digital converter 601 ressdc sinus/digital-converter resolu- tion 12 bit 602 aaabs absolute angular accuracy vpp() = 4 v, adjusted -0.35 0.35 deg 603 aarel relative angular accuracy with reference to one output periode at a, b, at resolution 1024, see fig. 17 -10 10 % 604 f()ab output frequency at a, b cfgmtb = 0 0.5 mhz cfgmtb = 1 2.0 mhz 605 rescom resolution of commutation con- verter 1.875 deg 606 aaabs absolute angular accuracy of commutation converter -0.5 0.5 deg serial interface, digital outputs ma, slo, sli 701 vs(slo)hi saturation voltage high v(slo) = v(vpd) ? v(), i(slo) = 4 ma 0.4 v 702 vs(slo)lo saturation voltage low i(slo) = 4 ma to vnd 0.4 v 703 isc(slo)hi short-circuit current high v(slo) = v(vnd), 25c -80 -50 ma 704 isc(slo)lo short-circuit current low v(slo) = v(vpd), 25c 50 80 ma 705 tr(slo) rise time slo cl = 50 pf 60 ns 706 tf(slo) fall time slo cl = 50 pf 60 ns 707 vt()hi threshold voltage high: ma, sli 2 v 708 vt()lo threshold voltage low: ma, sli 0.8 v 709 vt()hys threshold hysteresis: ma, sli 150 250 mv 710 ipd(sli) pull-up current: ma, sli v() = 0...vpd ? 1 v 6 30 60 a 711 ipu(ma) -60 -30 -6 a 712 f()ma 10 mhz zapping and test 801 vt()hi threshold voltage high vzap, pte with reference to vnd 2 v 802 vt()lo threshold voltage low vzap, pte with reference to vnd 0.8 v 803 vt()hys hysteresis vt()hys = vt()hi ? vt()lo 150 250 mv 804 vt()nozap threshold voltage nozap vzap v() = v(vzap) ? v(vpd), v(vpd) = 5 v 5 %, at chip temperature 27 c 0.8 v 805 vt()zap threshold voltage zap vzap v() = v(vzap) ? v(vpd), v(vpd) = 5 v 5 %, at chip temperature 27 c 1.2 v 806 v()zap zapping voltage prog = 1 6.9 7.0 7.1 v 807 v()zpd diode voltage, zapped 2 v 808 v()uzpd diode voltage, unzapped 3 v 809 rpd()vzap pull-down resistor at vzap 30 55 k nerr output 901 vt()hi input threshold voltage high with reference to vnd 2 v 902 vs()lo saturation voltage low i() = 4 ma , with reference to vnd 0.4 v 903 vt()lo input threshold voltage low with reference to vnd 0.8 v 904 vt()hys input hysteresis vt()hys = vt()hi ? vt()lo 150 250 mv 905 ipu(nerr) pull-up current v(nerr) = 0...vpd ? 1 v -700 -300 -80 a 906 isc()lo short circuit current nerr v(nerr) = v(vpd), 25c 50 80 ma 907 tf(nerr) decay time nerr cl = 50 pf 60 ns
ic-mh 12 bit angular hall encoder rev b1, page 6/ 23 electrical characteristics operating conditions: vpa, vpd = 5 v 10 %, tj = -40...125 c, ibm adjusted to 200 a , 4 mm ndfeb magnet, unless otherwise noted item symbol parameter conditions unit no. min. typ. max. line driver outputs p01 vs()hi saturation voltage hi vs() = vpd ? v(); cfgdr(1:0) = 00, i() = -4 ma 200 mv cfgdr(1:0) = 01, i() = -50 ma 700 mv cfgdr(1:0) = 10, i() = -50 ma 700 mv cfgdr(1:0) = 11, i() = -20 ma 400 mv p02 vs()lo saturation voltage lo cfgdr(1:0) = 00, i() = -4 ma 200 mv cfgdr(1:0) = 01, i() = -50 ma 700 mv cfgdr(1:0) = 10, i() = -50 ma 700 mv cfgdr(1:0) = 11, i() = -20 ma 400 mv p03 isc()hi short-circuit current hi v() = 0 v; cfgdr(1:0) = 00 -12 -4 ma cfgdr(1:0) = 01 -120 -50 ma cfgdr(1:0) = 10 -120 -50 ma cfgdr(1:0) = 11 -60 -20 ma p04 isc()lo short-circuit current lo v() = vpd; cfgdr(1:0) = 00 4 12 ma cfgdr(1:0) = 01 50 120 ma cfgdr(1:0) = 10 50 120 ma cfgdr(1:0) = 11 20 60 ma p05 ilk()tri leakage current tristate trihl(1:0) = 11 -100 100 a p06 tr() rise-time lo to hi at q rl = 100 to vnd; cfgdr(1:0) = 00 5 20 ns cfgdr(1:0) = 01 5 20 ns cfgdr(1:0) = 10 50 350 ns cfgdr(1:0) = 11 5 40 ns p07 tf() fall-time hi to lo at q rl = 100 to vnd; cfgdr(1:0) = 00 5 20 ns cfgdr(1:0) = 01 5 20 ns cfgdr(1:0) = 10 50 350 ns cfgdr(1:0) = 11 5 40 ns operating requirements: serial interface operating conditions: vpa, vpd = 5 v 10 %, ta = -40...125 c, ibm calibrated to 200 a; logic levels referenced to vnd: lo = 0...0.45 v, hi = 2.4 v...vpd item symbol parameter conditions unit no. min. max. ssi protocol (enssi = 1) i001 t mas permissible clock period t out determined by cfgtos 250 2x t out ns i002 t mash clock signal hi level duration 25 t out ns i003 t masl clock signal lo level duration 25 t out ns figure 1: i/o interface timing with ssi protocol
ic-mh 12 bit angular hall encoder rev b1, page 7/ 23 registers overview adr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hall signal conditioning 0x00 z gaing(1:0) gainf(5:0) 0x01 z enac gcc(6:0) 0x02 z - voss(6:0) 0x03 z prm vosc(6:0) 0x04 z hclh dpu - cfgtob cibm(3:0) rs422 driver 0x05 z enssi cfgprot cfgo(1:0) trihl(1:0) cfgdr(1:0) sine/digital converter 0x06 z cfgres(7:0) 0x07 z cfgzpos(7:0) 0x08 z cfghys(1:0) cfgdir cfgmtd cfgsu cfgpole cfgab(1:0) 0x09 z cfgcom(7:0) 0x0a z - cfgmtd2 0x0b z - 0x0c z - 0x0d - test settings 0x0e p test(7:0) 0x0f - res. res. res. - - - progzap zap diodes (read only) 0x10 .. 0x1f zap dioden for adresses 0x00..0x0c und 0x7d..0x7f not used 0x20 .. 0x41 invalid adresses pro?le identi?cation (read only) 0x42 pro?le - 0x2c 0x43 pro?le - 0x0 data length dlen not used 0x44 .. 0x75 invalid adress status messages (read only; messages will be set back during reading) 0x76 gain 0x77 progerr errsdata erramin erramax errext res. res. progok
ic-mh 12 bit angular hall encoder rev b1, page 8/ 23 overview adr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 identi?cation (0x78 bis 0x7b read-only) 0x78 device id - 0x4d (m) 0x79 device id - 0x48 (h) 0x7a revision - 0x5a (z) 0x7b revision - 0x00 () 0x7c - cfgtos 0x7d z manufacturer revision - 0x00 0x7e z manufacturer id - 0x00 0x7f z manufacturer id - 0x00 z : register value programmable by zapping p : register value write protected; can only be changed while v(vzap)> vt()hi table 5: register layout hall signal processing . . . . . . . . . . . . . . . . . . . . page 10 gaing: hall signal ampli?cation range gainf: hall signal ampli?cation (1C20, log. scale) gcc: ampli?cation calibration cosine enac: activation of amplitude control voss: offset calibration sine vosc: offset calibration cosine prm: energy-saving mode cibm: calibration of bias current dpu deactivation of nerr pull-up hclh activation of high hall clock pulse rs422 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 18 cfgdr: driver property trihl: tristate high-side/low-side driver cfgo: con?guration of output mode cfgprot: write/read protection memory enssi: activation of ssi mode sine/digital converter . . . . . . . . . . . . . . . . . . . . . page 16 cfgres: resolution of sine digital converter cfgzpos: zero point for position cfgab: con?guration of incremental output cfgpole: no. of poles for commutation signals cfgsu: behavior during start-up cfgmtd: frequency at ab cfgdir: rotating direction reversal cfghys: hysteresis sine/digital converter cfgcom: zero point for commutation test test: test mode progzap: activation of programming routine
ic-mh 12 bit angular hall encoder rev b1, page 9/ 23 sensor principle figure 2: sensor principle in conjunction with a rotating permanent magnet, the ic-mh module can be used to create a complete en- coder system. a diametrically magnetized, cylindri- cal permanent magnet made of neodymium iron boron (ndfeb) or samarium cobalt (smco) generates op- timum sensor signals. the diameter of the magnet should be in the range of 3 to 6 mm. the ic-mh has four hall sensors adapted for angle determination and to convert the magnetic ?eld into a measurable hall voltage. only the z-component of the magnetic ?eld is evaluated, whereby the ?eld lines pass through two opposing hall sensors in the oppo- site direction. figure 2 shows an example of ?eld vec- tors. the arrangement of the hall sensors is selected so that the mounting of the magnets relative to ic-mh is extremely tolerant. two hall sensors combined pro- vide a differential hall signal. when the magnet is ro- tated around the longitudinal axis, sine and cosine out- put voltages are produced which can be used to deter- mine angles. position of the hall sensors and the analog sensor signal the hall sensors are placed in the center of the qfn28 package at 90 to one another and arranged in a circle with a diameter of 2 mm as shown in figure 3 . figure 3: position of the hall sensors when a magnetic south pole comes close to the sur- face of the package the resulting magnetic ?eld has a positive component in the +z direction (i.e. from the top of the package) and the individual hall sensors each generate their own positive signal voltage. in order to calculate the angle position of a diametri- cally polarized magnet placed above the device a dif- ference in signal is formed between opposite pairs of hall sensors, resulting in the sine being v sin = v psin - v nsin and the cosine v cos = v pcos - v ncos . the zero angle position of the magnet is marked by the resulting cosine voltage value being at a maximum and the sine voltage value at zero. this is the case when the south pole of the magnet is exactly above the pcos sensor and the north pole is above sensor ncos, as shown in figure 4 . sensors psin and nsin are placed along the pole boundary so that neither generate a hall signal. when the magnet is rotated counterclockwise the poles then also cover the psin and nsin sensors, re- sulting in the sine and cosine signals shown in figure 5 being produced. the signals are internal but can be made externally available for test purposes (see the description of ic-mhs calibration procedure). z y b -b z +b z x n s c151107-1 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 pin 1 mark psin pcos ncos nsin (top view) c040907-2
ic-mh 12 bit angular hall encoder rev b1, page 10/ 23 figure 4: zero position of the magnet figure 5: pattern of the analog sensor signals with the angle of rotation hall signal processing the ic-mh module has a signal calibration function that can compensate for the signal and adjustment errors. the hall signals are ampli?ed in two steps. first, the range of the ?eld strength within which the hall sensor is operated must be roughly selected. the ?rst ampli?er stage can be programmed in the follow- ing ranges: gaing(1:0) adr 0x00; bit 7:6 00 5-fold 01 10-fold 01 15-fold 01 20-fold table 6: range selection for hall signal ampli?cation the operating range can be speci?ed in advance in accordance with the temperature coef?cient and the magnet distance. the integrated amplitude control can correct the signal amplitude between 1 and 20 via an- other ampli?cation factor. should the control reach the range limits, a different signal ampli?cation must be se- lected via gaing. gainf(5:0) adr 0x00; bit 5:0 0x00 1,000 0x01 1,048 ... exp ( ln (20) 64 gainf ) 0x3f 19,08 table 7: hall signal ampli?cation the second ampli?er stage can be varied in an addi- tional range. with the amplitude control (enac = 0) deactivated, the ampli?cation in the gainf register is used. with the amplitude control (enac = 1) acti- vated, the gainf register bits have no effect. gcc(6:0) adr 0x01; bit 6:0 0x00 1,000 0x01 1,0015 ... exp ( ln (20) 2048 gcc ) 0x3f 1,0965 0x40 0,9106 ... exp ( ? ln (20) 2048 (128 ? gcc )) 0x7f 0,9985 table 8: ampli?cation calibration cosine the gcc register is used to correct the sensitivity of the sine channel in relation to the cosine channel. the cosine amplitude can be corrected within a range of approximately 10%. enac adr 0x01; bit 7 0 amplitude control deactivated 1 amplitude control active table 9: activation of amplitude control the integrated amplitude control can be activated with the enac bit. in this case the differential signal am- plitude is adjusted to 4 vss and the values of gainf have no effect here. n s 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 c040907-1 n s n s 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 2 2 3 2 4 2 5 2 6 2 7 2 8 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 8 9 9 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 2 1 2 0 1 9 1 8 1 7 1 6 1 5 2 1 2 0 1 9 1 8 1 7 1 6 1 5 0 a > 0 a = 0 a v = v - v sin psin nsin v = v - v cos pcos ncos +2v -2v 360 90 180 270 -90 (top view) c041007-3
ic-mh 12 bit angular hall encoder rev b1, page 11/ 23 figure 6: de?nition of differential amplitude after switch-on the ampli?cation is increased until the setpoint amplitude is reached. the ampli?cation is automatically corrected in case of a change in the input amplitude by increasing the distance between the magnet and the sensor, in case of a change in the supply voltage or a temperature change. the sine signals are therefore always converted into high- resolution quadrature signals at the optimum ampli- tude. voss(6:0) adr 0x02; bit 6:0 vosc(6:0) adr 0x03; bit 6:0 0x00 0 mv 0x01 1 mv ... ... 0x3f 63 mv 0x40 0 mv 0x41 -1 mv ... ... 0x7f -63 mv table 10: offset calibration for sine and cosine should there be an offset in the sine or cosine signal that, among other things, can also be caused by an inexactly adjusted magnet, then this offset can be cor- rected by the voss and vosc registers. the output voltage can be shifted by 63 mv in each case to com- pensate for the offset. prm adr 0x03; bit 7 0 energy-saving mode deactivated 1 energy-saving mode active table 11: energy-saving mode in the energy-saving mode the current consumption of the hall sensors can be quartered. this also reduces the maximum rotating frequency by a factor of 4. cibm(3:0) adr 0x04; bit 3:0 0x0 -40 % ... ... 0x8 0 % 0x9 +5 % ... ... 0xf +35 % table 12: calibration of bias current in the test mode (test = 0x43) the internal currents can be calibrated on pin b. for this purpose, the cur- rent must be measured based on vna and the cibm register bits must be changed until the current is cal- ibrated to 200 a. all internal currents are then cali- brated. hclh adr 0x04; bit 7 0 250 khz 1 500 khz table 13: activation of high hall clock pulse the switching-current hall sensors can be operated at two frequencies. at 500 khz the sine has twice the number of support points. this setting is of interest at high speeds above 30,000 rpm. pcos?ncos psin?nsin 4vss
ic-mh 12 bit angular hall encoder rev b1, page 12/ 23 test modes for signal calibration for signal calibration ic-mh has several test settings which make internal reference quantities and the am- pli?ed hall voltages of the individual sensors accessi- ble at external pins a, b, z and u for measurement pur- poses. this enables the settings of the offset (voss, vosc), gain (gaing, gainf) and amplitude ratio of the cosine to the sine signal (gcc) to be directly ob- served on the oscilloscope. test mode can be triggered by connecting pin vzap to vpd and programming the test register (address 0x0e). the individual test modes are listed in the fol- lowing table: output signals in test mode mode test pin a pin b pin z pin u normal 0x00 a b z u analog sin 0x20 hpsp hpsn hnsp hnsn analog cos 0x21 hpcp hpcn hncp hncn analog out 0x22 psin nsin pcos ncos analog ref 0x43 vref ibm vbg vosr digital clk 0xc0 clkd table 14: test modes and available output signals the output voltages are provided as differential sig- nals with an average voltage of 2.5 v. the gain is de- termined by register values gaing and gainf and should be set so that output amplitudes from the sine and cosine signals of about 1 v are visible. test modes analog sin and analog cos in these test modes it is possible to measure the sig- nals from the individual hall sensors independent of one another. the name of the signal is derived from the sensor name and position. hpsp , for example, is the (ampli?ed) h all voltage of sensor ps in at the p ositive signal path; similarly, hncn is the h all voltage of sensor nc os at the n egative signal path. the effec- tive hall voltage is accrued from the differential voltage between the positive and negative signal paths of the respective sensor. test mode analog out in this test mode the sensor signals are available at the outputs as they would be when present internally for further processing on the interpolator. the interpo- lation accuracy which can be obtained is determined by the quality of signals v sin and v cos and can be in?u- enced in this particular test mode by the calibration of the offset, gain and amplitude ratio. figure 7: output signals of the sine hall sensors in test mode analog sin figure 8: output signals of the cosine hall sensors in test mode analog cos figure 9: differential sine and cosine signals in test mode analog out test mode analog ref in this mode various internal reference voltages are provided. vref is equivalent to half the supply voltage (typically 2.5 v) and is used as a reference voltage for the hall sensor signals. vbg is the internal bandgap a b z u b b b b h a l l s e n s o r s v n a ic-mh psin v psin nsin h p s p h p s n h n s p h n s n v nsin test mode: analog sin c021107-1 a b z u b b b b h a l l s e n s o r s v n a ic-mh v pcos ncos h p c p h p c n h n c p h n c n v ncos test mode: analog cos pcos c021107-2 a b z u b b b b h a l l s e n s o r s v n a ic-mh v sin ncos p s i n n s i n p c o s n c o s v cos test mode: analog out pcos psin nsin c021107-3
ic-mh 12 bit angular hall encoder rev b1, page 13/ 23 reference (1.24 v), with vosr (0.5 v) used to gener- ate the range of the offset settings. bias current ibm determines the internal current setting of the analog circuitry. in order to compensate for variations in this current and thus discrepancies in the characteristics of the individual ic-mh devices (due to ?uctuations in production, for example), this can be set within a range of -40% to +35% using register parameter cibm. the nominal value of 200 a is measured as a short-circuit current at pin b to ground. test mode digital clk if, due to external circuitry, it is not possible to mea- sure ibm directly, by way of an alternative clock signal clkd at pin a can be calibrated to a nominal 1 mhz in this test mode via register value cibm. figure 10: setting bias current ibm in test mode analog ref calibration procedure the calibration procedure described in the following applies to the optional setting of the internal analog sine and cosine signals and the mechanical adjust- ment of the magnet and ic-mh in relation to one an- other. bias setting the bias setting compensates for possible manufac- turing tolerances in the ic-mh devices. a magnetic ?eld does not need to be present for this setting which can thus be made either prior to or during the assem- bly of magnet and ic-mh. if the optional setup process is not used, register cibm should be set to an average value of 0x8 (which is equivalent to a change of 0%). as described in the previous section, by altering the value in register cibm in test mode analog ref current ibm is set to 200 a or, alternatively, in test mode digital clk signal clkd is set to 1 mhz. mechanical adjustment ic-mh can be adjusted in relation to the magnet in test modes analog sin and analog cos, in which the hall signals of the individual hall sensors can be observed while the magnet rotates. in test mode analog sin the output signals of the sine hall sensors which are diagonally opposite one an- other are visible at pins a, b, z and u. ic-mh and the magnet are then adjusted in such a way that differen- tial signals v psin and v nsin have the same amplitude and a phase shift of 180. the same applies to test mode analog cos, where differential signals v pcos and v ncos are calibrated in the same manner. figure 11: ideal lissajous curve calibration using analog signals in test mode analog out as shown in figure 5 the in- ternal signals which are transmitted to the sine/digital converter can be tapped with high impedance. with a rotating magnet it is then possible to portray the dif- ferential signals v sin and v cos as an x-y graph (lis- sajous curve) with the help of an oscilloscope. in an ideal setup the sine and cosine analog values describe a perfect circle as a lissajous curve, as illustrated by figure 11 . at room temperature and with the amplitude control switched off (enac = 0) a rough gaing setting is se- lected so that at an average ?ne gain of gainf = 0x20 (a gain factor of ca. 4.5) the hall signal amplitudes are as close to 1 v as possible. the amplitude can then be set more accurately by varying gainf. variations in a b z u v n a ic-mh i b m v b g ~ 2 0 0 a ~ 2 .5 v v o s r test mode: analog ref ~ 1 .2 4 v ~ 0 .5 v v r e f c021107-4 v cos v sin a +2 v -2 v -2 v +2 v c141107-1
ic-mh 12 bit angular hall encoder rev b1, page 14/ 23 the gain factor, as shown in figure 12 , have no effect on the lissajous curve, enabling the angle information for the interpolator to be maintained. figure 12: effect of gain settings gaing and gainf deviations of the observed lissajous curve from the ideal circle can be corrected by varying the ampli- tude offset (register voss, vosc) and amplitude ratio (register gcc). changes in these parameters are de- scribed in the following ?gures 13 to 15 . each of these settings has a different effect on the interpolated angle value. a change in the sine offset thus has a maximum effect on the angle value at 0 and 180, with no al- terations whatsoever taking place at angles of 90 and 270. when varying the cosine offset exactly the oppo- site can be achieved as these angle pairs can be set independent of one another. setting the cosine/sine amplitude ratio does not change these angles (0, 90, 180 and 270); however, in-between values of 45, 135, 225 and 315 can still be in?uenced by this pa- rameter. once calibration has been carried out a signal such as the one illustrated in figure 11 should be available. in the ?nal stage of the process the amplitude control can be switched back on (enac =1) to enable devi- ations in the signal amplitude caused by variations in the magnetic ?eld due to changes in distance and tem- perature to be automatically controlled. figure 13: effect of the sine offset setting figure 14: effect of the cosine offset setting figure 15: effect of the amplitude ratio v cos v sin a gaing gainf c141107-2 v cos v sin a voss c141107-3 v cos v sin a vosc c141107-4 v cos v sin a gcc c141107-5
ic-mh 12 bit angular hall encoder rev b1, page 15/ 23 calibration using incremental signals if test mode cannot be used, signals can also be cali- brated using the incremental signals or the values read out serially. in order to achieve a clear relationship be- tween the calibration parameters which have an effect on the analog sensor signals and the digital sensor val- ues derived from these, the position of the zero pulse should be set to zpos = 0 so that the digital signal starting point matches that of the analog signals. at an incremental resolution of 8 edges per revolu- tion (cfgres = 0x1) those angle values can be dis- played at which calibration parameters voss, vosc and gcc demonstrate their greatest effect. when ro- tating the magnet at a constant angular speed the in- cremental signals shown in figure 16 are achieved, with which the individual edges ideally succeed one another at a temporal distance of an eighth of a cy- cle (a 45 angle distance). alternatively, the angle po- sition of the magnet can also be determined using a reference encoder, rendering an even rotational action unnecessary and allowing calibration to be performed using the available set angle values . the various possible effects of parameters voss, vosc and gcc on the ?ank position of incremental signals a and b are shown in figure 16 . ideally, the distance of the rising edge (equivalent to angle posi- tions of 0 and 180) at signal a should be exactly half a period (per). should the edges deviate from this in distance, the offset of the sine channel can be adjusted using voss. the same applies to the falling edges of the a signal which should also have a distance of half a period; deviations can be calibrated using the offset of cosine parameter vosc. with parameter gcc the distance between the neighboring ?anks of signals a and b can then be adjusted to the exact value of an eighth of a cycle (a 45 angle distance). figure 16: calibration using incremental signals
ic-mh 12 bit angular hall encoder rev b1, page 16/ 23 sine/digital converter the ic-mh module integrates two separate sine/digital converters. a high-resolution 12-bit converter for the abz incremental signals can be programmed in broad ranges of the resolution and generate quadrature sig- nals even at the highest speed and resolution. the converter operates for the commutation signals inde- pendently of this and can be set in the zero point sep- arately from the quadrature converter. this enables the commutation at other angles based on the index track z. cfgres(7:0) adr 0x06; bit 7:0 0x0 1 0x1 2 ... ... 0x7e 127 0x7f 128 0x80 256 0x81 512 0x82 1024 table 15: programming interpolation factor the resolution of the 12-bit converter can virtually be set as desired. any resolution can be set up to an in- terpolation factor of 128, i.e. 512 edges per rotation. at higher resolutions, only the binary resolutions can be set, i.e. 256, 512 and 1024. in the highest resolution with an interpolation factor of 1024, 4096 edges per rotation are generated and 4096 angular steps can be differentiated. even in the highest resolution, the abso- lute position can be calculated in real time at the maxi- mum speed. after the resolution is changed, a module reset is triggered internally and the absolute position is recalculated. cfgab(1:0) adr 0x08; bit 1:0 0x0 a and b not inverted 0x1 b inverted, a normal 0x2 a inverted, b normal 0x3 a and b inverted table 16: inversion of ab signals figure 17: abz signals and relative accuracy the incremental signals can be inverted again inde- pendently of the output drivers. as a result, other phase angles of a and b relative to the index pulse z can be generated. the standard is a and b high level for the zero point, i.e. z is equal to high . figure 17 shows the position of the incremental sig- nals around the zero point. the relative accuracy of the edges to each other at a resolution setting of 10 bit is better than 10%. this means that, based on a period at a or b, the edge occurs in a window between 40% and 60%. cfghys(1:0) adr 0x08; bit 7:6 0x0 0,17 0x1 0,35 0x2 0,7 0x3 1,4 table 17: programming angular hysteresis with rotating direction reversal, an angular hysteresis prevents multiple switching of the incremental signals at the reversing point. the angular hysteresis corre- sponds to a slip which exists between the two rotating directions. however, if a switching point is approached from the same direction, then the edge is always gen- erated at the same position on the output. the fol- lowing ?gure shows the generated quadrature signals for a resolution of 360 edges per rotation (interpolation factor 90) and a set angular hysteresis of 1.4. 40%50% 60% ab z 100%
ic-mh 12 bit angular hall encoder rev b1, page 17/ 23 figure 18: quadrature signals for rotating direction reversal (hysteresis 1.4) at the reversal point at +10, ?rst the corresponding edge is generated at a. as soon as an angle of 1.4 has been exceeded in the other direction in accor- dance with the hysteresis, the return edge is generated at a again ?rst. this means that all edges are shifted by the same value in the rotating direction. cfgzpos(7:0) adr 0x07; bit 7:0 0x0 0 0x1 1,4 0x2 2,8 ... 360 256 cfgzpos 0xff 358,6 table 18: programming ab zero position the position of the index pulse z can be set in 1.4 steps. an 8-bit register is provided for this purpose, which can shift the z-pulse once over 360. cfgmtd2 cfgmtd minimum edge spacing 0 0 500 ns max. 500 khz at a 0 1 125 ns max. 2 mhz at a 1 0 8 s max. 31.25 khz at a 1 1 2 s max. 125 khz at a table 19: minimum edge spacing the cfgmtb register de?nes the time in which two consecutive position events can be output. the de- fault is a maximum output frequency of 500 khz on a. this means that at the highest resolution, speeds of 30,000 rpms can still be correctly shown. in the set- ting with an edge spacing of 125 ns, the edges can be generated even at the highest revolution and the max- imum speed. however, the counter connected to the module must be able to correctly process all edges in this case. the settings with 2 s, and 8 s can be used for slower counters. it should be noted then, however, that at higher resolutions the maximum rotation speed is reduced. cfgdir adr 0x08; bit 5 0 rotating direction ccw 1 rotating direction cw table 20: rotating direction reversal the rotating direction can easily be changed with the bit cfgdir. when the setting is ccw (counter- clockwise, cfgdir = 0) the resulting angular position values will increase when rotation of the magnet is per- formed as shown in ?gure 5 . to obtain increasing an- gular position values in the cw (clockwise) direction, cfgdir then has to be set to 1. the internal analoge sine and cosine signal which are available in test mode are not affected by the setting of cfgdir. they will always appear as shown in ?gure 5 . cfgsu adr 0x08; bit 3 0 abz output "111" during startup 1 ab instantly counting to actual position table 21: con?guration of output startup depending on the application, a counter cannot bear generated pulses while the module is being switched on. when the supply voltage is being connected, ?rst the current position is determined. during this phase, the quadrature outputs are constantly set to "111" in the setting cfgsu = 0. in the setting cfgsu = 1, edges are generated at the output until the absolute position is reached. this enables a detection of the absolute position with the incremental interface. the converter for the generation of the commutation signals can be con?gured for two and four-pole mo- tors. three rectangular signals each with a phase shift of 120 are generated. with two-pole commutation, the sequence repeats once per rotation. with a four-pole setting, the commutation sequence is generated twice per rotation. cfgpole adr 0x8; bit 1 0 2 pole commutation 1 4 pole commutation table 22: commutation the zero position of the commutation, i.e. the rising edge of the track u, can be set as desired over a rota- tion. here 192 possible positions are available. values above 0xc0 are the mirrored positions from 0x70. cfgpole(7:0) adr 0x09; bit 7:0 0x00 0 0x01 1,875 ... 360 192 cfgcom 0xbf 358,125 table 23: commutation ?10 0 10 0 0 1.4 ab z
ic-mh 12 bit angular hall encoder rev b1, page 18/ 23 output drivers six rs422-compatible output drivers are available, which can be con?gured for the incremental signals and commutation signals. the following table on the cfgo register bits provides an overview of the possi- ble settings. cfgo(1:0) adr 0x07; bit 7:6 00 incrementral diff abz (u=na, v=nb, w=nz) 01 incr abz + comm uvw 10 commutation diff uvw (a=nu, b=nv, z=nw) 11 incr. abz + ab4 (u=a4, v=b4, w=0) table 24: con?guration of output drivers in the differential incremental mode (cfgo = 00, fig- ure 19 ), quadrature signals are available on the pins a, b and z. the respective inverted quadrature sig- nals are available on the pins u, v and w. as a result, lines can be connected directly to the module. another con?guration of the incremental signals is speci?ed in the section "sine/digital converter". with cfgo = 01 (figure 20 ) the abz incremental sig- nals and the uvw commutation signals are available on the six pins. as long as the current angular posi- tion is not yet available during the start-up phase, all commutation signals are at the low level. with cfgo = 10, the third mode (figure 21 ) is avail- able for transferring the commutation signals via a dif- ferential line. the non-inverted signals are on the pins u, v and w, the inverted signals on a, b and z. the abz quadrature signals with an adjustable higher resolution and quadrature signals with one period per rotation are available in the fourth mode (figure 22 ). four segments can be differentiated with the pins u and v. this information can be used for an external period counter which counts the number of scanned complete rotations. figure 19: abz differential incremental signals figure 20: abz incremental / uvw commutation signals figure 21: uvw differential commutation signals figure 22: abz incremental signals / period counter z ic?mh b a pcos psin uv w z ic?mh b au v w pcos psin ic?mh psin pcos ab z u v w z ic?mh b a pcos psin w uv
ic-mh 12 bit angular hall encoder rev b1, page 19/ 23 the property of the rs422 driver of the connected line can be adjusted in the cfgdr register. cfgdr(1:0) adr 0x07; bit 1:0 00 10 mhz 4 ma (default) 01 10 mhz 60 ma 10 300 khz 60 ma 11 3 mhz 20 ma table 25: driver property signals with the highest frequency can be transmitted in the setting cfgdr = 00. the driver capability is at least 4 ma, however it is not designed for a 100 line. this mode is ideal for connection to a digital in- put on the same assembly. with the setting cfgdr = 01 the same transmission speed is available and the driver power is suf?cient for the connection of a line over a short distance. steep edges on the output enable a high transmission rate. a lower slew rate is offered by the setting cfgdr = 10, which is excel- lent for longer lines in an electromagnetically sensitive environment. use of the setting cfgdr = 11 is advis- able at medium transmission rates with a limited driver capability. trihl adr 0x07; bit 3:2 00 push pull output stage 01 lowside driver 10 highside driver 11 tristate table 26: tristate register the drivers consist of a push-pull stage in each case with low-side and high-side drivers which can each be activated individually. as a result, open-drain outputs with an external pull-up resistor can also be realized. serial interface the serial interface is used to read out the absolute position and to parameterize the module. for a de- tailed description of the protocol, see separate inter- face speci?cation. figure 23: serial interface protocol the sensor sends a ?xed cycle-start sequence con- taining the acknowledge-, start and control-bit fol- lowed by the binary 12 bit sensor data. at lower resolu- tion settings the data word contains leading zeros. the low-active error bit ne a 0 indicates an error which can be further identi?ed by reading the status register 0x77. the following bit nw is always at 1 state. fol- lowing the 6 crc bits the data of the next sensors, if available, are presented. otherwise, the master stops generating clock pulse on the ma line an the sensor runs into a timeout, indicating the end of communica- tion. serial interface protocol mode c cycle start sequence ack/start/cds lenght of sensor data 12 bit + err + warn crc polynom 0b1000011 crc mode inverted multi cycle data not available max. data rate 10 mhz table 27: interface protocol enssi adr 0x05; bit 7 0 extended ssi-mode 1 ssi-mode table 28: activation of ssi mode in the ssi mode the absolute position is output with 13 bits according to the ssi standard. however, in the ssi cds start d10 d11 cdm stop ack d0 ne nw crc4 crc0 ma sli slo data range timeout crc5
ic-mh 12 bit angular hall encoder rev b1, page 20/ 23 mode it is not possible to vary the parameter set. the data is transmitted as reduced gray code, e.g. after converting into binary code, the data range is symmet- rical to the center of the number string. for example, with a set resolution of 360 data values between 76 and 435 are transmitted. figure 24: ssi protocol, data gray-coded the register range 0x00 to 0x0f is equivalent to the settings with which the ic can be parameterized. the settings directly affect the corresponding switching parts. it is important to note that test register 0x0e can only be written to when pin vzap is connected to vpd. when vpd > 6 v, write access to the test register is ig- nored. register 0x0f can be con?gured at potentials v(vzap) > vt(vzap)hi. the range 0x10 to 0x1f is read-only and re?ects the contents of the integrated zapping diodes. following programming the data can be veri?ed via these ad- dresses. after the supply voltage is connected, the contents of the zapping diodes are copied to the ram area 0x00 to 0x0f. then the settings can be overwrit- ten via the serial interface. overwriting is not possible if the cfgprot bit is set. errors in the module are signaled via the error mes- sage output nerr. this open-drain output signals an error if the output is pulled against vnd. if the er- ror condition no longer exists, then the pin is released again after a waiting time of approximately 1 ms. if the integrated pull-up resistor is deactivated with dpu = 1, then an external resistor must be provided. with dpu = 0 it brings the pin up to the high level again. dpu adr 0x04; bit 6 0 pull-up activated 1 pull-up deactive table 29: activation of nerr pull-up with the pro?le id, the data format can be requested for the following sensor data cycles in the module. a read operation at address 0x42 results in 0x2c, with is the equivalent to 12-bit single-cycle data. the register 0x43 which follows now contain the data length dlen of the transmitted sensor data in accordance with the set resolution. the sensor data are transmitted right- justi?ed and ?lled with preceding zeros if necessary. the following table shows the data length according to the resolution. dlen adr 0x43; bit 3:0 2 cfgres = 00000000, 4 3 cfgres = 00000001, 8 4 cfgres = 0000001x, 12 to 16 5 cfgres = 000001xx, 20 to 32 6 cfgres = 00001xxx, 36 to 64 7 cfgres = 0001xxxx, 68 to 128 8 cfgres = 001xxxxx, 132 to 256 9 cfgres = 01xxxxxx, 260 to 512 10 cfgres = 10000000, 1024 11 cfgres = 10000001, 2048 12 cfgres = 10000010, 4096 table 30: data length the status register provides information on the status of the module. there are 5 different errors that can be signaled. following unsuccessful programming of the zapping diodes, the bit progerr is set. if an attempt is made to read the current position via the se- rial interface during the start-up phase, an error is sig- naled with errsdata, as the actual position is not yet known. the erramax bit is output to signal that the amplitude is too high, while the erramin bit signals an amplitude which is too low, caused, for example, by too great a distance to the magnet. if the nerr pin is pulled against vnd outside the module, this error is also signaled via the serial interface. the errext bit is then equal to 1. the error bits are reset again after the status register is read out at the address 0x77. the error bit in the data word is then also read in the next cycle as 0. cfgtos cfgtob timeout 0 0 16 s 1 0 2 s x 1 2 s table 31: timeout for sensor data the timeout can be programmed to a shorter value with the cfgtos bit. however, this setting is reset to the default value 16 s again following a reset. the timeout can be permanently programmed for faster data transmission with the cfgtob register via a zap- ping diode. resetting to slower data transmission is then not possible. the registers 0x7d to 0x7f are reserved for the man- ufacturer and can be provided with an id so that the manufacturer can identify its modules
ic-mh 12 bit angular hall encoder rev b1, page 21/ 23 otp programming cfgprot adr 0x05; bit 6 0 no protection 1 write/read protection table 32: write/read protection of con?guration with cfgprot = 0, the registers at the addresses 0x00 to 0x0f and 0x78 to 0x7f are readable and write- able. the addresses 0x10 to 0x1f and 0x77 are read- only. with cfgprot = 1, all registers except the ad- dresses 0x7b and 0x7c are write-protected; the ad- dresses 0x77 to 0x7f are readable, while all others are read-protected. figure 25: programming within system an internal programming algorithm for the zap diodes is started by setting the bit progzap. this process can only be successful, if the voltage difference be- tween vzap and vna pin is within the speci?ed value and the test register is set to test = 0x00. following programming, the progzap bit is reset automatically. in the process, the bit progok is set in the status reg- ister (address 0x77) when programming is successful, and the bit progerr, if it is not. a 100 nf ceramic block capacitor must be placed on board directly between vzap and vna pins of the ic- mh. also a 10 f capacitor must be present at the end of the programming line as close to the connec- tor as possible (see ?gure 25 ). during programming up to 100 ma ?ow from pin vzap to pin vna, making it necessary to ensure proper pcb layout to minimize voltage drops. figure 26: programming algorithm once the device has been successfully calibrated the con?guration can be written into the device. to this end the contents of the ram bits are transferred to the rom zapping structure. cibm is ?rst set to 0x0 at address 0x04 and the hardware programming algo- rithm started by bit progzap. programming should be monitored with the threshold settings for cibm and vpd, vpa voltage by reading out the zap structures via the serial interface. if programming is not success- ful, the hardware programming algorithm can again be initiated. in the second stage of the procedure the bias current is programmed in the cibm register. here, all ram bits are set to 0x00; register cibm is con?gured with the calculated calibration value and the program- ming algorithm started. programming is successful when all bits have been con?gured. ic-mh vzap vpd vpa vna vnd sli slo ma programming board +7v +5v 0v 10uf 100nf 100nf serial interface 100nf + start stop set configuration start hw zap algorithm set adr 0x0f = 0x01 vpd = vpa = 5.0v verify vpd = vpa = 5.5v cibm = 0x0 verify vpd = vpa = 4.0v cibm = 0xf false true false true cibm programmed? true false set cibm = 0x0 set cibm
ic-mh 12 bit angular hall encoder rev b1, page 22/ 23 this speci?cation is for a newly developed product. ic-haus therefore reserves the right to change or update, without notice, any information contained herein, design and speci?cation; and to discontinue or limit production or distribution of any product versions. please contact ic-haus to ascertain the current data. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the speci?cation on this site and does not assume liability for any errors or omissions in the materials. the data speci?ed is intended solely for the purpose of product description. no representations or warranties, either express or implied, of merchantability, ?tness for a particular purpose or of any other nature are made hereunder with respect to information/speci?cation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. as a general rule our developments, ips, principle circuitry and range of integrated circuits are suitable and speci?cally designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. in principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the bureau of statistics in wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in hanover (hannover-messe). we understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
ic-mh 12 bit angular hall encoder rev b1, page 23/ 23 ordering information type package order designation ic-mh qfn28 ic-mh qfn28 ic-mh eval mh1d for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (61 35) 92 92-0 am kuemmerling 18 fax: +49 (61 35) 92 92-192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.de/support_distributors.php

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